Project Zipline - a high throughput, low latency lossless compression engine that using the innovation XP10 algorithm.

https://github.com/opencomputeproject/Project-Zipline

#compression #huffman #lz77 #zipline #XP10 #verilog #SV #lossless

net2axis - network traffic verilog module for simulation: from pcap to AXI-Stream.

net2axis (simulation-only Verilog module) generates Master AXI-Stream transactions from network packets described in packet capture files (PCAP). It provides a convenient way for a user to develop his/hers network hardware design by simulating a Network/Ethernet/MAC/Internet Protocol IP cores.

Description, Sources

#verilog #PCAP #AXIS #network #simulation

USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

Current solutions for USB3 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A) or external FIFO (FTDI FT60X or Cypress FX3). With this project, we want to see if it's possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip).

https://github.com/enjoy-digital/usb3_pipe

#USB3 #PIPE #PHY #verilog #LiteX #python #Xilinx #Lattice

OpenOFDM - implementation of 802.11 OFDM decoder.

In a nutshell, the top level dot11 Verilog module takes 32-bit I/Q samples (16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling rate is 20 MSPS and the clock rate is 100 MHz.

Features:
◦ Full support for legacy 802.11a/g
◦ Support 802.11n for MCS 0..7@20MHz bandwidth
◦ Cross validation with included Python decoder

https://github.com/jhshi/openofdm

#verilog #OFDM #PHY #802.11 #USRP #WiFi

Nyuzi - an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like deep learning and image processing.

This GPGPU includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

High level features:
◦ Multiple cores with cache coherence
◦ Hardware multithreading
◦ Wide vector floating point SIMD with predicated execution
◦ Virtual memory

src: https://github.com/jbush001/NyuziProcessor
doc: https://github.com/jbush001/NyuziProcessor/wiki

#SV #GPGPU #FPGA #LLVM

Open Source USB test suite is an open source test suite for USB IP cores. It currently supports USB1.1 and will be extended for higher revisions in the future.

◦ https://github.com/antmicro/usb-test-suite-build - top level repo
◦ https://github.com/antmicro/usb-test-suite-cocotb-usb - cocotb_usb
◦ https://github.com/antmicro/usb-test-suite-testbenches - test and wrapper scripts

#verification #cocotb #python #USB #tb

HDMI Out - SystemVerilog code for HDMI 1.4a video/audio output on an FPGA. To support audio and other HDMI-only functionality, a true HDMI signal must be sent. The code in this repository lets you do that without having to license an HDMI IP block from anyone.

◦ 24-bit color
◦ Data island packets
◦ Null packet
◦ ECC with BCH systematic encoding GF(2^8)
◦ Audio clock regeneration
◦ L-PCM audio 2-channel
◦ Audio InfoFrame
◦ Video formats 1, 2, 3, 4, 16, 17, 18, 19
◦ VGA text mode
◦ IBM 8x16 font
◦ Double Data Rate I/O (DDRIO)
◦ Supports up to 1920x1080@60Hz

https://github.com/hdl-util/hdmi

#HDMI #Altera #SystemVerilog

ScopeIO - Embedded Measurement System in the FPGA that lets you see as much data as you need using as few resources as possible.

Features:
◦ Small footprint to embed it
◦ Portability
◦ VGA to display data
◦ BRAM requirement only
◦ DDR core to capture high speed data
◦ UDP to communicate with host

Links:
◦ sources
◦ docs
◦ slides

#debug #simulation #VHDL #oscilloscope

MIPI CSI Camera Sensor Receiver implementation. Tested with IMX219 on Lattice MachXO3LF.

https://github.com/circuitvalley/mipi_csi_receiver_FPGA

#MIPI #CSI #video #verilog

MIPI DSI Bridge: Controller Firmware code receiving images from PC (over USB) and transmitting over SPI to FPGA. Tested with LH154Q01-TD01 LCD 240x240 1.54 inch (Apple IPOD nano 6G) on Lattice MachXO3LF.

◦ sources
◦ description

#MIPI #DSI #video #verilog

DVB_FPGA - RTL implementation of components for DVB-S2 (initially focusing on the transmission side).

Features:
◦ AXI-Stream interfaces
◦ Frame types: Normal and short
◦ Constellations: 8 PSK, 16 APSK and 32 APSK
◦ Code rates: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10

Components done:
◦ Baseband scrambler
◦ BCH encoder
◦ Bit interleaver
Components todo:
◦ Constellation mapper
◦ LDPC Encoder
◦ Physical layer framing

https://github.com/phase4ground/dvb_fpga

#VHDL #DVB #AXI #LDPC

Ibex - a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.

Ibex is ideally suited as control core in many embedded scenarios. Ibex is a high-quality core: together with the RTL, lowRISC provides full UVM-based verification, extensive documentation and all the tools to successfully integrate Ibex into designs.

Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.

◦ Sources
◦ Docs

#ISA #RISCV #SystemVerilog #SV #CPU #LowRISC

FastVDMA - fast, vendor-neutral DMA IP in Chisel. This DMA controller designed with portability and customizability in mind.

The purpose of a DMA controller is to arbitrate and handle the transfer of blocks of data directly from an I/O device to the main memory of a system, with minimal intervention of the CPU.

The main feature of FastVDMA is the ability to support multiple types of buses, namely AXI4, AXI-Stream and Wishbone. Each one of these buses can be used as write or read frontends.

Features:
◦ Interrupts
◦ 2D transfers with configurable stride
◦ External frame synchronization inputs

Links:
◦ Description
◦ Sources

#DMA #chisel #AXI #wishbone

FPGA USB Bootloader - an open source IP for programming FPGAs without extra USB interface chips.

It implements a USB virtual serial port to SPI flash bridge on the FPGA fabric itself. For FPGAs that support loading multiple configurations it is possible for the bootloader to be completely unloaded from the FPGA before the user configuration is loaded in. From the host computer's perspective, the bootloader looks like a serial port.

Links:
◦ Device side
◦ Host side

#USB #bootloader #FPGA #verilog

Lightweigth USB Core - core that would be similar to the SIE you find in classic microcontrollers that support USBs. That means it requires a soft core to implement the actual USB stack, the hardware itself only handle up to the transaction layer of USB.

It's designed to be small but still allow full flexibility of what kind of device it implements, supports all types of transfers, all packet sizes and any combination of end points without having to change the hardware configuration at all.

Features:
◦ 10 BRAM, 390 FF and 530 LUT4
◦ Clocked at 48 MHz
◦ Wishbone interface for the CSRs and Buffer Descriptors

Links:
◦ Doc
◦ Src

#USB #iCE40 #FPGA #verilog #PHY

MIPI I3C Basic v1.0 - implementation of I3C Slave in Verilog with BSD license to support use in sensors and other devices.

Features:
◦ I3C SDR protocol
◦ All required CCCs plus some optional ones
◦ IBI (in band interrupt) including optional IBI data byte
◦ Support for I2C with a static address
◦ Two different integrations depending on system:
◦ Full APB memory mapped registers for processor based systems
◦ Autonomous model for state machine ASICs

Note: this version does not include HDR-DDR, HDR-Ternary, Time-control, nor Master support. It also lacks some other advanced features including for i2c.

https://github.com/NXP/i3c-slave-design

#I3C #I2C #verilog #MIPI

Verilog PCI-Express Components

Collection of PCI express related components. Includes PCIe to AXI and AXI lite bridges, a simple PCIe AXI DMA engine, and a flexible, high-performance DMA subsystem. Currently supports operation with the Xilinx Ultrascale and Ultrascale+ PCIe hard IP cores with interfaces between 64 and 512 bits. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

◦ Doc
◦ Src

#PCIE #verilog #MyHDL #AXI #BFM #xilinx #DMA

Piplined FFT Core - configurable C++ generator of Verilog FFT cores.

The FFT generated by this project is very configurable. By simple adjustment of a command line parameter, the FFT created will either be a forward FFT or an inverse FFT. The number of bits processed, kept, and maintained by this FFT are also configurable. Even the number of bits used for the twiddle factors, or whether or not to bit reverse the outputs, are all configurable parts to this FFT core.

https://github.com/ZipCPU/dblclockfft

#DSP #FFT #generator #verilog

A2I POWER Processor Core from IBM POWER team now open.
100% in pure VHDL

https://github.com/openpower-cores/a2i

#IBM #OpenPOWER #VHDL #FO4