Display Controller project written in verilog and supports VGA, DVI, and HDMI displays. It includes full configuration for 640x480, 800x600, 1280x720, and 1920x1080, as well as the ability to define custom resolutions. TMDS Encoder model already included in src.

https://github.com/projf/display-controller

#HDMI #DVI #TMDS #SerDes #VGA #verilog #Xilinx

ARM provide easy access to Cortex-M Soft Processor IP on Xilinx FPGA.

DesignStart FPGA offers instant and free access to Cortex-M1 and Cortex-M3 soft CPU IP for use on Xilinx FPGA designs for prototypes and commercial deployments.

The Cortex-M1 and Cortex-M3 processor IP is at full release quality (REL) and suitable for mass deployment. The example systems, board support package and tool integration are released at beta with updates and improvements on an ongoing basis.

Link (registration required)

#ARM #Xilinx #Cortex #CPU #DesignStart

The AMBA Bus Protocol Assertions is a verification and validation product designed to work with a range of different user environments and usage scenarios. The underlying goal is to provide protocol specific SystemVerilog assertions for the AMBA v3 & v4: ACE, AXI3, AXI4, AXI4-Lite and AXI4-Stream protocols.

Features:
◦ Support for the latest version of the AXI Specification
◦ Support for separate parameterisation for read and write ID widths
◦ Enhancements to end of simulation checks

This release has been developed and tested:
◦ SystemVerilog v3.1a
◦ Mentor ModelSim SE 10.1a
◦ Cadence Incisive 11.10.008
◦ Synopsys VCS 2011.12-3

Download links:
◦ AMBA 3 AXI3 Protocol Assertions
◦ AMBA 4 AXI4 Protocol Assertions
◦ AMBA 4 ACE Protocol Checker
◦ [All downloads required registration]

#AMBA #AXI #AXIlite #AXIS #SVA #SV #BFM #verification #ProtocolChecker

BOOM - an open-source out-of-order RISC-V CPU (RV64G ISA).
Like most contemporary high-performance cores, BOOM is superscalar (able to execute multiple instructions per cycle) and out-of-order (able to execute instructions as their dependencies are resolved and not restricted to their program order).

The main features of BOOMv2:
◦ updated 3-stage front-end design with a bigger set-associative Branch Target Buffer (BTB)
◦ pipelined register rename stage
◦ split floating point and integer register files
◦ dedicated floating point pipeline
◦ separate issue windows for floating point, integer, and memory micro-operations
◦ separate stages for issue-select and register read

Links:
◦ Sources
◦ Publication
◦ Presentation

#RISCV #RV64 #out-of-order #scala #chisel #CPU #BOOM

Project Zipline - a high throughput, low latency lossless compression engine that using the innovation XP10 algorithm.

https://github.com/opencomputeproject/Project-Zipline

#compression #huffman #lz77 #zipline #XP10 #verilog #SV #lossless

net2axis - network traffic verilog module for simulation: from pcap to AXI-Stream.

net2axis (simulation-only Verilog module) generates Master AXI-Stream transactions from network packets described in packet capture files (PCAP). It provides a convenient way for a user to develop his/hers network hardware design by simulating a Network/Ethernet/MAC/Internet Protocol IP cores.

Description, Sources

#verilog #PCAP #AXIS #network #simulation

USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

Current solutions for USB3 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A) or external FIFO (FTDI FT60X or Cypress FX3). With this project, we want to see if it's possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip).

https://github.com/enjoy-digital/usb3_pipe

#USB3 #PIPE #PHY #verilog #LiteX #python #Xilinx #Lattice

OpenOFDM - implementation of 802.11 OFDM decoder.

In a nutshell, the top level dot11 Verilog module takes 32-bit I/Q samples (16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling rate is 20 MSPS and the clock rate is 100 MHz.

Features:
◦ Full support for legacy 802.11a/g
◦ Support 802.11n for MCS 0..7@20MHz bandwidth
◦ Cross validation with included Python decoder

https://github.com/jhshi/openofdm

#verilog #OFDM #PHY #802.11 #USRP #WiFi

Nyuzi - an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like deep learning and image processing.

This GPGPU includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

High level features:
◦ Multiple cores with cache coherence
◦ Hardware multithreading
◦ Wide vector floating point SIMD with predicated execution
◦ Virtual memory

src: https://github.com/jbush001/NyuziProcessor
doc: https://github.com/jbush001/NyuziProcessor/wiki

#SV #GPGPU #FPGA #LLVM

Open Source USB test suite is an open source test suite for USB IP cores. It currently supports USB1.1 and will be extended for higher revisions in the future.

◦ https://github.com/antmicro/usb-test-suite-build - top level repo
◦ https://github.com/antmicro/usb-test-suite-cocotb-usb - cocotb_usb
◦ https://github.com/antmicro/usb-test-suite-testbenches - test and wrapper scripts

#verification #cocotb #python #USB #tb

HDMI Out - SystemVerilog code for HDMI 1.4a video/audio output on an FPGA. To support audio and other HDMI-only functionality, a true HDMI signal must be sent. The code in this repository lets you do that without having to license an HDMI IP block from anyone.

◦ 24-bit color
◦ Data island packets
◦ Null packet
◦ ECC with BCH systematic encoding GF(2^8)
◦ Audio clock regeneration
◦ L-PCM audio 2-channel
◦ Audio InfoFrame
◦ Video formats 1, 2, 3, 4, 16, 17, 18, 19
◦ VGA text mode
◦ IBM 8x16 font
◦ Double Data Rate I/O (DDRIO)
◦ Supports up to 1920x1080@60Hz

https://github.com/hdl-util/hdmi

#HDMI #Altera #SystemVerilog

ScopeIO - Embedded Measurement System in the FPGA that lets you see as much data as you need using as few resources as possible.

Features:
◦ Small footprint to embed it
◦ Portability
◦ VGA to display data
◦ BRAM requirement only
◦ DDR core to capture high speed data
◦ UDP to communicate with host

Links:
◦ sources
◦ docs
◦ slides

#debug #simulation #VHDL #oscilloscope

MIPI CSI Camera Sensor Receiver implementation. Tested with IMX219 on Lattice MachXO3LF.

https://github.com/circuitvalley/mipi_csi_receiver_FPGA

#MIPI #CSI #video #verilog

MIPI DSI Bridge: Controller Firmware code receiving images from PC (over USB) and transmitting over SPI to FPGA. Tested with LH154Q01-TD01 LCD 240x240 1.54 inch (Apple IPOD nano 6G) on Lattice MachXO3LF.

◦ sources
◦ description

#MIPI #DSI #video #verilog

DVB_FPGA - RTL implementation of components for DVB-S2 (initially focusing on the transmission side).

Features:
◦ AXI-Stream interfaces
◦ Frame types: Normal and short
◦ Constellations: 8 PSK, 16 APSK and 32 APSK
◦ Code rates: 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10

Components done:
◦ Baseband scrambler
◦ BCH encoder
◦ Bit interleaver
Components todo:
◦ Constellation mapper
◦ LDPC Encoder
◦ Physical layer framing

https://github.com/phase4ground/dvb_fpga

#VHDL #DVB #AXI #LDPC

Ibex - a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture.

Ibex is ideally suited as control core in many embedded scenarios. Ibex is a high-quality core: together with the RTL, lowRISC provides full UVM-based verification, extensive documentation and all the tools to successfully integrate Ibex into designs.

Ibex offers several configuration parameters to meet the needs of various application scenarios. The options include two different choices for the architecture of the multiplier and divider unit, as well as the possibility to drop the support for the "M" extension completely. In addition, the "E" extension can be enabled when opting for a minimum-area configuration.

◦ Sources
◦ Docs

#ISA #RISCV #SystemVerilog #SV #CPU #LowRISC