Yet another solution (IP+driver) for DMA over PCI-E for Linux/Windows Xilinx/Altera. http://xillybus.com/ #DMA #PCI-E #RIFFA #Xillybus

Verilog implementation of DisplayPort protocol for FPGA

Resolution| Lanes |Eff.Pix.clock
----------+-------+-------------
800x600   |   1   |  40.00 MHz
800x600   |   2   |  40.00 MHz
800x600   |   3   |  40.00 MHz
1280x720  |   1   |  74.25 MHz
1920x1080 |   2   | 148.50 MHz
3240x2160 |   2   | 165.00 MHz

https://github.com/hamsternz/DisplayPort_Verilog

#DisplayPort #verilog #video #FullHD

BaseJump STL: A standard library for SystemVerilog

This library has many of the standard components that you use in hardware design. But these ones are nicely parameterized, and try to use latency-insensitive
interfaces where it does not hurt performance.

Available sources, paper and video

#SV #library #STL #primitives

VHDL-extras - provides some extra bits of code that are not found in the standard VHDL libraries. The VHDL-extras library contains 50+ components and many more utility functions that can enhance and simplify many hardware development tasks.

● Core packages
◦ pipelining – Pipeline registers
◦ sizing – Generalized integer logarithms and array size computation
◦ synchronizing – Clock domain synchronizing components
◦ timing_ops – Conversions for time, frequency, and clock cycles
● Arithmetic
◦ arithmetic – Pipelined adder
◦ bit_ops – Bitwise operations
◦ cordic – CORDIC rotation algorithm and Sine/Cosine generation
◦ filtering – Digital filters
● Signal processing
◦ ddfs – Direct Digital Frequency Synthesizer
◦ oscillator – Sinusoidal frequency generators
● Error handling
◦ crc_ops – Compute CRCs
◦ hamming_edac – Generalized Hamming error correction encoding and decoding
◦ parity_ops – Basic parity operations
◦ secded_edac – Hamming extension with double-error detection
● Encoding
◦ bcd_conversion – Encode and decode packed Binary Coded Decimal
◦ gray_code – Encode and decode Gray code
◦ muxing – Decoder and muxing operations
● Memories
◦ fifos – General purpose FIFOs
◦ memory – Synthesizable memories
◦ reg_file – General purpose register file
● Randomization
◦ lcar_ops – Linear Cellular Automata
◦ lfsr_ops – Linear Feedback Shift Registers
◦ random – Simulation-only random number generation
● Miscellaneous
◦ binaryio – Binary file I/O
◦ interrupt_ctl – General purpose priority interrupt controller
◦ text_buffering – Store text files in internal buffers
◦ glitch_filtering – Clean up noisy inputs


Docs and sources

#VHDL #library #primitives

OpenSource Hybrid Memory Cube Controller (meets HMC specification Rev 1.1).

Features
● Full link-training, sleep mode, and link retraining
● 16Byte up to 128Byte read and write transactions
● Posted and non-posted bit-write and atomic requests
● Mode Read and Write
● Full packet flow control
● Packet integrity checks (sequence number, packet length, CRC,...)
● Full automatic link retry

Configurations
● 2 FLITs per Word / 256-bit datapath
● 4 FLITs per Word / 512-bit datapath
● 6 FLITs per Word / 768-bit datapath
● 8 FLITs per Word / 1024-bit datapath


Sources, docs

#HMC #memory #SV

Wave Computing® Inc., the Silicon Valley company launches MIPS Open™, provides royalty-free access to chip design data. New Release of MIPSOpen Components Includes Verilog RTL Code for MIPS32 microAptiv Cores

The new set of MIPS Open program components will include two different versions of the microAptiv Verilog RTL code:

● microAptiv MCU core: designed with application-specific features and real-time performance for microcontroller SoC development
● microAptiv MPU core: includes a cache controller and MMU facilitating embedded system designs executing operating systems such as Linux

In addition to the Verilog RTL code, the package also includes documentation, configuration tools and a verification suite.
MIPS Open program components are available for immediate download

#MIPS #MIPS32 #MIPSOpen #microAptiv #microMIPS #RTL #verilog

Display Controller project written in verilog and supports VGA, DVI, and HDMI displays. It includes full configuration for 640x480, 800x600, 1280x720, and 1920x1080, as well as the ability to define custom resolutions. TMDS Encoder model already included in src.

https://github.com/projf/display-controller

#HDMI #DVI #TMDS #SerDes #VGA #verilog #Xilinx

ARM provide easy access to Cortex-M Soft Processor IP on Xilinx FPGA.

DesignStart FPGA offers instant and free access to Cortex-M1 and Cortex-M3 soft CPU IP for use on Xilinx FPGA designs for prototypes and commercial deployments.

The Cortex-M1 and Cortex-M3 processor IP is at full release quality (REL) and suitable for mass deployment. The example systems, board support package and tool integration are released at beta with updates and improvements on an ongoing basis.

Link (registration required)

#ARM #Xilinx #Cortex #CPU #DesignStart

The AMBA Bus Protocol Assertions is a verification and validation product designed to work with a range of different user environments and usage scenarios. The underlying goal is to provide protocol specific SystemVerilog assertions for the AMBA v3 & v4: ACE, AXI3, AXI4, AXI4-Lite and AXI4-Stream protocols.

Features:
◦ Support for the latest version of the AXI Specification
◦ Support for separate parameterisation for read and write ID widths
◦ Enhancements to end of simulation checks

This release has been developed and tested:
◦ SystemVerilog v3.1a
◦ Mentor ModelSim SE 10.1a
◦ Cadence Incisive 11.10.008
◦ Synopsys VCS 2011.12-3

Download links:
◦ AMBA 3 AXI3 Protocol Assertions
◦ AMBA 4 AXI4 Protocol Assertions
◦ AMBA 4 ACE Protocol Checker
◦ [All downloads required registration]

#AMBA #AXI #AXIlite #AXIS #SVA #SV #BFM #verification #ProtocolChecker

BOOM - an open-source out-of-order RISC-V CPU (RV64G ISA).
Like most contemporary high-performance cores, BOOM is superscalar (able to execute multiple instructions per cycle) and out-of-order (able to execute instructions as their dependencies are resolved and not restricted to their program order).

The main features of BOOMv2:
◦ updated 3-stage front-end design with a bigger set-associative Branch Target Buffer (BTB)
◦ pipelined register rename stage
◦ split floating point and integer register files
◦ dedicated floating point pipeline
◦ separate issue windows for floating point, integer, and memory micro-operations
◦ separate stages for issue-select and register read

Links:
◦ Sources
◦ Publication
◦ Presentation

#RISCV #RV64 #out-of-order #scala #chisel #CPU #BOOM

Project Zipline - a high throughput, low latency lossless compression engine that using the innovation XP10 algorithm.

https://github.com/opencomputeproject/Project-Zipline

#compression #huffman #lz77 #zipline #XP10 #verilog #SV #lossless

net2axis - network traffic verilog module for simulation: from pcap to AXI-Stream.

net2axis (simulation-only Verilog module) generates Master AXI-Stream transactions from network packets described in packet capture files (PCAP). It provides a convenient way for a user to develop his/hers network hardware design by simulating a Network/Ethernet/MAC/Internet Protocol IP cores.

Description, Sources

#verilog #PCAP #AXIS #network #simulation

USB3 PIPE interface for Xilinx 7-Series / Lattice ECP5

Current solutions for USB3 connectivity with an FPGA require the use of an external SerDes chip (TI TUSB1310A) or external FIFO (FTDI FT60X or Cypress FX3). With this project, we want to see if it's possible to just use the transceivers of the FPGA for the USB3 connectivity and have the USB3 PIPE directly implemented in the fabric (and then avoid any external chip).

https://github.com/enjoy-digital/usb3_pipe

#USB3 #PIPE #PHY #verilog #LiteX #python #Xilinx #Lattice

OpenOFDM - implementation of 802.11 OFDM decoder.

In a nutshell, the top level dot11 Verilog module takes 32-bit I/Q samples (16-bit each) as input, and output decoded bytes in 802.11 packet. The sampling rate is 20 MSPS and the clock rate is 100 MHz.

Features:
◦ Full support for legacy 802.11a/g
◦ Support 802.11n for MCS 0..7@20MHz bandwidth
◦ Cross validation with included Python decoder

https://github.com/jhshi/openofdm

#verilog #OFDM #PHY #802.11 #USRP #WiFi

Nyuzi - an experimental GPGPU processor hardware design focused on compute intensive tasks. It is optimized for use cases like deep learning and image processing.

This GPGPU includes a synthesizable hardware design written in System Verilog, an instruction set emulator, an LLVM based C/C++ compiler, software libraries, and tests. It can be used to experiment with microarchitectural and instruction set design tradeoffs.

High level features:
◦ Multiple cores with cache coherence
◦ Hardware multithreading
◦ Wide vector floating point SIMD with predicated execution
◦ Virtual memory

src: https://github.com/jbush001/NyuziProcessor
doc: https://github.com/jbush001/NyuziProcessor/wiki

#SV #GPGPU #FPGA #LLVM

Open Source USB test suite is an open source test suite for USB IP cores. It currently supports USB1.1 and will be extended for higher revisions in the future.

◦ https://github.com/antmicro/usb-test-suite-build - top level repo
◦ https://github.com/antmicro/usb-test-suite-cocotb-usb - cocotb_usb
◦ https://github.com/antmicro/usb-test-suite-testbenches - test and wrapper scripts

#verification #cocotb #python #USB #tb

HDMI Out - SystemVerilog code for HDMI 1.4a video/audio output on an FPGA. To support audio and other HDMI-only functionality, a true HDMI signal must be sent. The code in this repository lets you do that without having to license an HDMI IP block from anyone.

◦ 24-bit color
◦ Data island packets
◦ Null packet
◦ ECC with BCH systematic encoding GF(2^8)
◦ Audio clock regeneration
◦ L-PCM audio 2-channel
◦ Audio InfoFrame
◦ Video formats 1, 2, 3, 4, 16, 17, 18, 19
◦ VGA text mode
◦ IBM 8x16 font
◦ Double Data Rate I/O (DDRIO)
◦ Supports up to 1920x1080@60Hz

https://github.com/hdl-util/hdmi

#HDMI #Altera #SystemVerilog