HyperRAM Controller from Intel
Cyclone® 10LP: around 300 LEs, 2 M9Ks, up to 166MHz
https://www.intel.com/content/www/us/en/programmable/solutions/partners/partner-profile/a-l-s-e/ip/hyperram-controller.html

#HyperRAM #verilog #Cypress #ISSI

Collections of #MIPI related IP-cores on #Verilog:

#CSI
CSI-2 receiver for Xilinx UltraScale [https://github.com/stevenbell/csirx]
4k CSI-2 Rx core for Xilinx FPGA [https://github.com/daveshah1/CSI2Rx]

#DSI
Lattice iCE40UP FPGA to LH154Q01 Display [https://github.com/gtjennings1/UPDuino-LH154Q01-Display]
Arduino MIPI DSI Shield [https://github.com/twlostow/dsi-shield]

SystemVerilog FIFO and CDC-components

https://github.com/runsler/library
#SV #FIFO #resynchronization #CDC

FPGA implementation of true random generator on Self-timed Rings.
Maximum speed for best random quality is 0.5 Mbit/s.

https://github.com/esynr3z/strng
https://ieeexplore.ieee.org/document/7332773
#RNG #TRNG #random #verilog

DDR3 memory controller that does not depend on any non-documented features of Xilinx FPGA and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted modules. Everything in plain Verilog and constraints.

https://github.com/Elphel/eddr3
https://blog.elphel.com/2014/06/ddr3-memory-interface-on-xilinx-zynq-soc-free-software-compatible/
#DDR3 #Xilinx #AXI

USB3 core:
USB2/ULPI & USB3/PIPE are working.

The design currently uses a TUSB1310A for interfacing with the USB3.0 connector. Future plans include replacing this part using the high speed transceivers (GTPs/GTXs) found in Artix-7/Kintex-7 FPGAs.

https://github.com/enjoy-digital/daisho

#USB2 #USB3 #verilog #TUSB1310A #Xilinx

PCIe DMA Engine for Xilinx FPGA

Its main purpose is to provide a simple Direct Memory Access (DMA) interface to the Xilinx Virtex-7 PCIe Gen3 hard block. Core is specifically designed for the 256 bit wide AXI4-Stream interface of the Xilinx FPGA HardBlock PCIe Gen3. Core has been also successfully ported to Xilinx Kintex UltraScale FPGA.

https://opencores.org/projects/virtex7_pcie_dma

#PCIe #DMA #Xilinx #VHDL #AXIS
@ipcores

FlexPRET is a 5-stage, fine-grained multithreaded #RISCV processor designed specifically for mixed-criticality (real-time embedded) systems and written in #Chisel

https://github.com/pretis/flexpret
@ipcores

PonyLink - a bi-directional chip-to-chip interface that is using only a single signal wire between the two chips. Naturally this wire is used in a half-duplex fashion. For faster link speeds the use of a #LVDS pair is recommended. The cores are tested on #Xilinx Series 7 and #Lattice iCE40 FPGAs.

On the chip-facing side #PonyLink provides a transmit and receive #AXI Stream as well as 8 GPIO inputs and 8 GPIO outputs. PonyLink handles all the low-level tasks, including flow control and detection of failed transfers and automatic resend.

The main features of the core are that it only requires one single data line between the chips and that it can operate on resonable data rates (compared to the clock rates of the clocks driving the cores, usually over 0.5 MBit/s per MHz).

Features:
- typical net data rates of over 100 MBit/s at 166 MHz
- can utilize up to 4x serdes hardware for higher link speed
- support for any #AXIS TDATA and TUSER width and TLAST signal
- bi-directional communication over a single data line (usually LVDS)
- works without a dedicated hardware block for clock recovery
- dc-free signaling, allowing for caps or magnetics in the link
- embedded clock and control signals (using #8b10b encoding)

https://github.com/cliffordwolf/PonyLink
https://github.com/cliffordwolf/PonyLink/blob/master/plinksrc/protocol.txt
#verilog #python #protocol #serialinterface
@ipcores

Digilent Vivado library contains free-to-use IP cores and interface definitions compatible with Xilinx Vivado IP Catalog.

https://github.com/Digilent/vivado-library

#vivado #ip #VHDL #verilog
@ipcores

VectorBlox ORCA is an implementation of RISC-V. It is intended to target FPGAs and can be configured as either #RV32I a #RV32IM core.

ORCA can be used as a standalone processor, but was built to be a host to Vectorblox's proprietary Lightweight Vector Extensions (LVE) or full-fledged Matrix processor MXP.

It has optional #AXI3/4 instruction and data caches, a separate #AXI4-Lite interface for uncached transactions, and an auxiliary interface that can be configured as either #WISHBONE, Intel #Avalon, or Xilinx #LMB.

https://github.com/VectorBlox/orca

#VHDL #RISCV @ipcores

FPGALink - Library for JTAG-programming and subsequently interacting with an FPGA over USB using a microcontroller (primarily the Cypress FX2LP). It allows you to:

* Load and save Cypress FX2LP firmware
* Communicate with the FPGA using HiSpeed USB (~25Mbyte/s)
* Reprogram the FPGA using JTAG over USB
* Bootstrap an FPGA design standalone using minimal components

https://github.com/makestuff/libfpgalink
https://github.com/makestuff/libfpgalink/wiki/FPGALink

#USB #FX2LP #FIFO #Interface #VHDL #verilog @ipcores

Simple framework for building PCIe-based solutions for Altera FPGAs, including Linux driver & userspace examples, the requisite Altera PCIe core and supporting logic, and a simple DMA controller

https://github.com/makestuff/altera-pcie

#Altera #PCIE #DMA #Linux #SV

Open-source RISC-V from Bluespec, Inc; this is one of a family of free, open-source RISC-V CPUs.

* Piccolo: 3-stage, in-order pipeline: Piccolo is intended for low-end applications (Embedded Systems, IoT, microcontrollers, etc.).

* Flute: 5-stage, in-order pipeline: Flute is intended for low-end to medium applications that require 64-bit operation, an MMU (Virtual Memory) and more performance than Piccolo-class processors.

* Tooba: superscalar, out-of-order pipeline: slight variation on MIT's RISCY-OOO [In progress!]

* Bassoon: deep, out-of-order pipeline: [Coming!]

https://github.com/bluespec/Piccolo
https://github.com/bluespec/Flute
https://github.com/bluespec/Toooba
https://github.com/bluespec/Bassoon

#Verilog #RISCV #BlueSpec #BSV #AXI4
@ipcores

GLIP is a solution for transferring data through FIFOs between a host, usually a PC, and a target, usually a HW-component such as an FPGA or a microcontroller. The actual data transport can happen through various interfaces, such as USB 3.0, JTAG or TCP. GLIP encapsulates all low-level details of the data transfers and provides on the host side an easy to use C library, and on the target side ready to use interfaces to quickly setup a working communication.

https://www.glip.io/
https://github.com/TUM-LIS/glip

#GLIP #Cypress #FX2LP #FX3 #verilog #OprenOCD #JTAG #FT2232 #UART #linux
@ipcores

LISNoC is a free Network-on-Chip implementation, mainly for academic or teaching purposes (but freely available for any use under the MIT license).
It is a straight forward implementation with follow basic features:
∙ Virtual channel support
∙ Flexible router configuration (number of input ports, number of output ports,..)
∙ Wormhole routing, strict ordering
∙ Round-robin arbitration for link multiplexing

http://www.lisnoc.org/
https://github.com/TUM-LIS/lisnoc

#NoC #router #interconnect #verilog
@ipcores

Reusable Integration Framework for FPGA Accelerators (RIFFA) is a simple framework for communicating data from a host CPU to a FPGA via a PCI-E. RIFFA supports Windows/Linux, Altera/Xilinx, with bindings for C/C++, Python, MATLAB and Java.

https://github.com/KastnerRG/riffa
#PCI-E #DMA #Linux

Yet another solution (IP+driver) for DMA over PCI-E for Linux/Windows Xilinx/Altera. http://xillybus.com/ #DMA #PCI-E #RIFFA #Xillybus

Verilog implementation of DisplayPort protocol for FPGA

Resolution| Lanes |Eff.Pix.clock
----------+-------+-------------
800x600   |   1   |  40.00 MHz
800x600   |   2   |  40.00 MHz
800x600   |   3   |  40.00 MHz
1280x720  |   1   |  74.25 MHz
1920x1080 |   2   | 148.50 MHz
3240x2160 |   2   | 165.00 MHz

https://github.com/hamsternz/DisplayPort_Verilog

#DisplayPort #verilog #video #FullHD

BaseJump STL: A standard library for SystemVerilog

This library has many of the standard components that you use in hardware design. But these ones are nicely parameterized, and try to use latency-insensitive
interfaces where it does not hurt performance.

Available sources, paper and video

#SV #library #STL #primitives

VHDL-extras - provides some extra bits of code that are not found in the standard VHDL libraries. The VHDL-extras library contains 50+ components and many more utility functions that can enhance and simplify many hardware development tasks.

● Core packages
◦ pipelining – Pipeline registers
◦ sizing – Generalized integer logarithms and array size computation
◦ synchronizing – Clock domain synchronizing components
◦ timing_ops – Conversions for time, frequency, and clock cycles
● Arithmetic
◦ arithmetic – Pipelined adder
◦ bit_ops – Bitwise operations
◦ cordic – CORDIC rotation algorithm and Sine/Cosine generation
◦ filtering – Digital filters
● Signal processing
◦ ddfs – Direct Digital Frequency Synthesizer
◦ oscillator – Sinusoidal frequency generators
● Error handling
◦ crc_ops – Compute CRCs
◦ hamming_edac – Generalized Hamming error correction encoding and decoding
◦ parity_ops – Basic parity operations
◦ secded_edac – Hamming extension with double-error detection
● Encoding
◦ bcd_conversion – Encode and decode packed Binary Coded Decimal
◦ gray_code – Encode and decode Gray code
◦ muxing – Decoder and muxing operations
● Memories
◦ fifos – General purpose FIFOs
◦ memory – Synthesizable memories
◦ reg_file – General purpose register file
● Randomization
◦ lcar_ops – Linear Cellular Automata
◦ lfsr_ops – Linear Feedback Shift Registers
◦ random – Simulation-only random number generation
● Miscellaneous
◦ binaryio – Binary file I/O
◦ interrupt_ctl – General purpose priority interrupt controller
◦ text_buffering – Store text files in internal buffers
◦ glitch_filtering – Clean up noisy inputs


Docs and sources

#VHDL #library #primitives