SURF (SLAC Ultimate RTL Framework) - a huge VHDL library for FPGA development.

Links:
▫️ sources
▫️ documentation

#VHDL #library #STL #primitives
@ipcores

open5G_rx - a synthesizable verilog HDL core for a 5G NR lower phy receiver.

Implemented:
▫️ Decimator
▫️ PSS correlator
▫️ Peak detector
▫️ PSS detector
▫️ FFT demodulator
▫️ SSS detector
▫️ Frame sync
▫️ Channel estimator
▫️ Ressource grid subscriber
▫️ AXI-DMAC


💾 https://github.com/catkira/open5G_rx

#SV #5G #DSP #FFT #ORAN
@ipcores

openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design.

Features:
▫️802.11a/g/n [IEEE 802.11n (Wi-Fi 4)]
▫️20MHz bandwidth; 70 MHz to 6 GHz frequency range
▫️Mode tested: Ad-hoc; Station; AP, Monitor
▫️DCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)
▫️802.11 packet injection and fuzzing
▫️CSI: Channel State Information, freq offset, equalizer to computer
▫️CSI fuzzer: Create artificial channel response in WiFi transmitter
▫️CSI radar: Moving detection. Joint radar and communication
▫️IQ capture: real-time AGC, RSSI, IQ sample to computer
▫️Configurable channel access priority parameters
▫️Time slicing based on MAC address (time gated/scheduled FPGA queues)
▫️Easy to change bandwidth and frequency:
▫️2MHz for 802.11ah
▫️10MHz for 802.11p

Links:
📄 https://github.com/open-sdr/openwifi
💾 https://github.com/open-sdr/openwifi-hw

#SV #80211 #SDR #DSP #wifi
@ipcores

SlowDDR3 - A general slow DDR3 interface.

Features:
▫️Very little resource consumption*
▫️Suits for all FPGAs with 1.5V IO voltage
▫️Designed to run at DDR-100
▫️Designed to work with LVCMOS IO PADs
▫️Write in SpinalHDL (Future is coming 😅)

*E.g. Gowin DDR3 IP consumes 1288 FFs, 1363 LUTs, 102 ALUs, 8 BSRAMs and 110 SSRAMs.
While slowDDR3 consumes 147 FFs and 216 LUTs.

Links:
💾 src: https://github.com/ZiyangYE/General-Slow-DDR3-Interface
📄 example: https://github.com/ZiyangYE/LicheeTang20K_DDR_Test

#DDR3 #SDRAM #SpinalHDL
@ipcores

USB_CDC - Full Speed (12Mbit/s) USB communications device class (or USB CDC class) for FPGA and ASIC designs.

USB_CDC implements the Abstract Control Model (ACM) subclass. Windows 10 provides a built-in driver (Usbser.sys) for USB CDC devices. A USB_CDC device is automatically recognized by Windows 10 as a virtual COM port, and a serial port terminal application such as CoolTerm can be used to communicate with it.

macOS and Linux provide built-in drivers for USB CDC ACM devices too. On macOS, the virtual COM gets a name like /dev/cu.usbmodem14601, whereas, on Linux, it gets a name like /dev/ttyACM0.

💾 https://github.com/ulixxe/usb_cdc

#USB #CDC #UART #verilog
@ipcores

USB_HID_host - a compact USB HID host FPGA core supporting keyboards, mice and gamepads.

It is designed mainly for FPGA retro gaming and computing projects. The most significant advantage is its all-in-one design. It does not require a CPU to work. And it is quite small (<300 LUTs, <250 registers and 1 BRAM block).

Features:
▫️No CPU is required. The core handles all layers of the USB protocol related to HID devices
▫️No USB interface IC (PHY) needed
▫️USB low-speed (1.5Mbps). Uses a single 12Mhz clock

💾 https://github.com/nand2mario/usb_hid_host

#USB #HID #host #verilog
@ipcores

FPGA USB-device - USB full-speed device core to implement. It requires only 3 FPGA common IOs rather than additional chips.

Features:
▫️Pure Verilog implementation
▫️Implementation of USB-serial, USB-MSD, USB-camera, USB-audio, USB-hid, etc
▫️The circuit is simple: three FPGA pins, one resistor and one USB connector

💾 https://github.com/WangXuan95/FPGA-USB-Device

#USB #HID #MSD #UVC #CDC #device #verilog
@ipcores

An FPGA-based 7-ENOB 600 MSample/s ADC without any External Components

In this work, a new structure of an FPGA-based ADC is proposed. The ADC is based on the slope ADC, where a time-to-digital converter (TDC) measures the time from the beginning of a reference slope until the slope reaches the voltage-to-be-measured.

Only FPGA-internal elements are used to build the ADC. It is fully reconfigurable and does not require any external components. This innovation offers the flexibility to convert almost any digital input/output (I/O) into an ADC.

The proposed ADC has a resolution of 9.3 bit and achieves an effective number of bits (ENOB) of 7 at a sample rate of 600 MSample/s. An alternative version of the ADC operates at 1.2 GSample/s and achieves an ENOB of 5.3.

Links:
💾 https://github.com/LukiLeu/FPGA_ADC
📄 https://dl.acm.org/doi/10.1145/3431920.3439287

#ADC #VHDL #TDC
@ipcores

Send video/audio over HDMI on an FPGA

SystemVerilog code for HDMI 1.4b video/audio output on an FPGA.

Features
▫️ 24-bit color
▫️ Data island packets
▫️ Null packet
▫️ ECC with BCH systematic encoding GF(2^8)
▫️ Audio clock regeneration
▫️ L-PCM audio 2-channel
▫️ Audio InfoFrame
▫️ Video formats 1, 2, 3, 4, 16, 17, 18, 19
▫️ VGA text mode
▫️ IBM 8x16 font
▫️ Double Data Rate I/O (DDRIO)
▫️ Supports up to 3840x2160@30Hz

Links
💾 https://github.com/hdl-util/hdmi
📄 https://purisa.me/blog/hdmi-released/

#HDMI #video #SV #SystemVerilog
@ipcores

FPGA-FFT - a highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

Features
▫️Data input/output are continuous with no gaps between frames
▫️Support power-of-two sizes
▫️Support fixed point data
▫️Resource usage is on par with Xilinx FFT IP core
▫️Fmax is up to 30% higher for common sizes than Xilinx FFT IP core

Links
💾 https://github.com/owocomm-0/fpga-fft

#fft #dsp #vhdl #xilinx
@ipcores

FPnew - New Parametric Floating-Point Unit with Transprecision Capabilities

Operations:
▫️Addition/Subtraction
▫️Multiplication
▫️Fused multiply-add in four flavours (fmadd, fmsub, fnmadd, fnmsub)
▫️Division
▫️Square root
▫️Minimum/Maximum
▫️Comparisons
▫️Sign-Injections (copy, abs, negate, copySign etc.)
▫️Conversions among all supported FP formats
▫️Conversions between FP formats and integers (signed & unsigned) and vice versa
▫️Classification

Links
💾 https://github.com/openhwgroup/cvfpu

#ieee754 #fp #floatingpoint
@ipcores

NNgen is an open-sourced compiler to synthesize a model-specific hardware accelerator for deep neural networks. NNgen generates a Verilog HDL source code and an IP-core package (IP-XACT) of a DNN accelerator from an input model definition.

Generated hardware is all-inclusive, which includes processing engine, on-chip memory, on-chip network, DMA controller, and control circuits. So the generated hardware does not require any additional controls from an external circuit or the CPU after the processing is started.

Links
💾 https://github.com/NNgen/nngen

#nn #onnx #dl #ml #compiler
@ipcores

Library that supports IEEE754-2008 floating point arithmetic with a parametrizable mantissa and exponent.

Features
▫️Fully parametrizable bit widths for exponent and mantissa
▫️Handles all special cases:
▪️ SNaN/QNaN
▪️ ± infinity
▪️ Denormalized numbers
▪️ Zeroes
▫️Single cycle operation
▫️Supports rounding to nearest (per official specification) or simply chopping bits

Links
💾 https://github.com/V0XNIHILI/parametrizable-floating-point-verilog

#IEEE754 #FP #arithmetic
@ipcores

Wupper - PCIe Gen3/Gen4/Gen5 DMA controller for Xilinx FPGA

Features
▫️Specifically designed for the 256/512/1024 bit wide AXI4-Stream interface
▫️Generic MSI-X compatible interrupt controller.
▫️Supporting PCIe Gen3, Gen4 and Gen5
▫️Supporting Series 7, UltraScale, Ultrascale+, Versal Prime and Versal Premium FPGAs

Links
💾 https://gitlab.nikhef.nl/franss/wupper/
📄 https://gitlab.nikhef.nl/franss/wupper/-/blob/master/documentation/wupper.pdf

#PCIE #DMA #Xilinx #FPGA #VHDL
@ipcores

FpOC - FPGA based Field Oriented Control (FOC) for driving Permanent Magnet Synchronous Motors (PMSM) or Brushless DC Motors (BLDC)

Features
▫️Support 3 channels of PWM + 1 channel of EN
▫️Supports angle sensor and phase current sampling ADC with 12bit resolution
▫️Internally uses 16bit signed integer for computation

Links
💾 https://github.com/WangXuan95/FPGA-FOC

#verilog #BLDC #PMSM #FOC #motor
@ipcores

fpga_linear_time_sorter - a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially

This algorithm is fast, since the sorting itself is done in parallel while the data is being input serially. It is sorted and ready to be read back immediately following the last write transfer.

A 256-length, 8-bit sorter costs approximately 5500 logical elements on an Altera Cyclone IV.

Links:
💾 https://github.com/Poofjunior/fpga_fast_serial_sort

#algo #sort #sorting
@ipcores

Floating Point Clock Divider is a 24.16 (m.n) bit floating point clock divider (actually it is a fixed point fractional divider).

Features
▫️Resulting frequency precision down to the 0.01Hz
▫️calculating PPM error
▫️calculating jitter spec

Links
💾 https://github.com/BrianHGinc/Verilog-Floating-Point-Clock-Divider
📄 https://www.eevblog.com/forum/fpga/verilog-floating-point-clock-divider-release/

#verilog #DIV #FP #clock #divider
@ipcores