🚀 Hewlett Packard Enterprise is Hiring – Cloud Developer
📍 Location: Bengaluru, Karnataka, India
🏢 Work Mode: Hybrid (2 Days/Week in Office)
💼 Role: Cloud Developer
🎯 Experience: 0–2 Years
🛠️ Key Skills:
• Python / Java / Golang / JavaScript
• Cloud Computing
• DevOps & CI/CD
• Microservices
• Distributed Systems
💰 Expected Salary: ₹8–18+ LPA (Estimated)
🎯 Best fit for:
• Freshers & Early Career Engineers
• Cloud Developers
• Software Engineers interested in Cloud & DevOps
• Backend Developers
✨ Work on cloud-native applications, distributed systems, DevOps pipelines, and next-generation edge-to-cloud solutions at HPE.
⚡ Apply as soon as possible!
🔗 Apply Here:
https://careers.hpe.com/us/en/job/1207454/Cloud-Developer?utm_source=linkedin
📍 Location: Bengaluru, Karnataka, India
🏢 Work Mode: Hybrid (2 Days/Week in Office)
💼 Role: Cloud Developer
🎯 Experience: 0–2 Years
🛠️ Key Skills:
• Python / Java / Golang / JavaScript
• Cloud Computing
• DevOps & CI/CD
• Microservices
• Distributed Systems
💰 Expected Salary: ₹8–18+ LPA (Estimated)
🎯 Best fit for:
• Freshers & Early Career Engineers
• Cloud Developers
• Software Engineers interested in Cloud & DevOps
• Backend Developers
✨ Work on cloud-native applications, distributed systems, DevOps pipelines, and next-generation edge-to-cloud solutions at HPE.
⚡ Apply as soon as possible!
🔗 Apply Here:
https://careers.hpe.com/us/en/job/1207454/Cloud-Developer?utm_source=linkedin
We are seeking highly skilled VLSI professionals to join our expanding team. Ideal candidates will have experience in:
- Design verification - SOC/ASIC/System Verilog/UVM/PCIe, Ethernet,DDR,AXI,AMBA - 5 to 20Years
- RTL Frontend design - ASIC/SOC - ASIC flow - /LINT/CDC/Synthesis/STA/High speed protocols/SOC integration- 6 to 15Years
- VLSI Technical Project/Program manager - RTL/DV/PD/Analog/Mixed signal - 10 to 15Years
- Post silicon validation ATE - V93K SMT7/8 OR Teradyne - ETS 364/J750/Ultraflex - 4 to 10Years
If you are passionate about cutting-edge semiconductor technologies, please email your profile to magenderan.r@hcltech.com.
- Design verification - SOC/ASIC/System Verilog/UVM/PCIe, Ethernet,DDR,AXI,AMBA - 5 to 20Years
- RTL Frontend design - ASIC/SOC - ASIC flow - /LINT/CDC/Synthesis/STA/High speed protocols/SOC integration- 6 to 15Years
- VLSI Technical Project/Program manager - RTL/DV/PD/Analog/Mixed signal - 10 to 15Years
- Post silicon validation ATE - V93K SMT7/8 OR Teradyne - ETS 364/J750/Ultraflex - 4 to 10Years
If you are passionate about cutting-edge semiconductor technologies, please email your profile to magenderan.r@hcltech.com.