#EC482
module BinaryAdderClkRst (A, B, Cin, clk, rst, SUM, Cout); input [3:0] A; input [3:0] B; input Cin; input clk; input rst; output [3:0] SUM; output Cout; reg [3:0] SUM; reg Cout; always @ (posedge clk or posedge rst) // ( Try Asynchronous / Synchronous reset, and note the different!) begin if (rst) begin SUM <= 0; Cout <= 0; end else begin {Cout,SUM} <= A + B + Cin; end end endmodule
_______________
`timescale 1ns/1ns module BinaryAdderClkRst_tb; reg [3:0] A; reg [3:0] B; reg Cin; reg clk; reg rst; wire [3:0] SUM; wire Cout; BinaryAdderClkRst UUT (.A(A), .B(B), .Cin(Cin), .clk(clk), .rst(rst), .SUM(SUM), .Cout(Cout)); always #10 clk = ~clk; initial begin A = 4'b0000; B = 4'b0000; Cin = 0; clk = 0; rst = 0; #80 A = 4'd15; // A = 15 #70 B = 4'd5; // B = 5 #90 Cin = 1; // Cin = 1 #70 rst = 1; // Assert reset #80 A = 4'd8; // A = 8 #80 B = 4'd10; // B = 10 #99 Cin = 0; // Cin = 0 #60 rst = 0; // Deassert reset #80 A = 4'd12; // A = 12 #70 B = 4'd7; // B = 7 #90 Cin = 1; // Cin = 1 #70 A = 4'd11; // A = 11 #90 B = 4'd9; // B = 9 #60 Cin = 1; // Cin = 1 #70 A = 4'd12; // A = 12 #50 B = 4'd6; // B = 6 #60 Cin = 0; // Cin = 0 #70 A = 4'd13; // A = 13 #50 B = 4'd4; // B = 4 #60 Cin = 1; // Cin = 1 #100 $finish; // End simulation end endmodule
module BinaryAdderClkRst (A, B, Cin, clk, rst, SUM, Cout); input [3:0] A; input [3:0] B; input Cin; input clk; input rst; output [3:0] SUM; output Cout; reg [3:0] SUM; reg Cout; always @ (posedge clk or posedge rst) // ( Try Asynchronous / Synchronous reset, and note the different!) begin if (rst) begin SUM <= 0; Cout <= 0; end else begin {Cout,SUM} <= A + B + Cin; end end endmodule
_______________
`timescale 1ns/1ns module BinaryAdderClkRst_tb; reg [3:0] A; reg [3:0] B; reg Cin; reg clk; reg rst; wire [3:0] SUM; wire Cout; BinaryAdderClkRst UUT (.A(A), .B(B), .Cin(Cin), .clk(clk), .rst(rst), .SUM(SUM), .Cout(Cout)); always #10 clk = ~clk; initial begin A = 4'b0000; B = 4'b0000; Cin = 0; clk = 0; rst = 0; #80 A = 4'd15; // A = 15 #70 B = 4'd5; // B = 5 #90 Cin = 1; // Cin = 1 #70 rst = 1; // Assert reset #80 A = 4'd8; // A = 8 #80 B = 4'd10; // B = 10 #99 Cin = 0; // Cin = 0 #60 rst = 0; // Deassert reset #80 A = 4'd12; // A = 12 #70 B = 4'd7; // B = 7 #90 Cin = 1; // Cin = 1 #70 A = 4'd11; // A = 11 #90 B = 4'd9; // B = 9 #60 Cin = 1; // Cin = 1 #70 A = 4'd12; // A = 12 #50 B = 4'd6; // B = 6 #60 Cin = 0; // Cin = 0 #70 A = 4'd13; // A = 13 #50 B = 4'd4; // B = 4 #60 Cin = 1; // Cin = 1 #100 $finish; // End simulation end endmodule
لا يوجد معمل هذا الاسبوع + يوجد محاضرة يوم الثلاثاء القادم و دكتورة هتزيد تبعتلنا غدا في حالة وجود توتوريال ام لا.
#EC381
#EC381
❤3