BiCMOS can be used in __________
a) amplifyig circuit
b) driver circuits c) divider circuit d) multiplier circuit

Factors significant in high speed semiconductors are
a) carrier mobility
b) carrier saturation velocity c) existence of semi-insulating substrate d) all of the mentioned

MESFET is a gallium arsenide device.
a) true
b) false

Second generation gallium arsenide device are
a) high electron mobility transistor
b) heterojunction bipolar transistor c) high electron mobility & heterojunction bipolar transistors d) none of the mentioned

Which device has very high speed?
a) CMOS
b) FET c) GaAs d) MESFET

The gallium arsenide field effect transistor is ________ majority carrier device.
a) bulk current insulation
b) bulk current conduction c) bulk voltage insulation d) bulk voltage conduction

How many masking stages does fabrication of GaAs FET require?
a) five
b) four c) ten d) eight

Which region is heavily doped?
a) drain
b) gate c) n-region d) p-region

Which is ON device?
a) e type MESFET
b) d type MESFET c) depletion d) enhancement

A highly doped thick channel exhibits _______ threshold voltage.
a) smaller negative
b) smaller positive c) larger negative d) larger positive

Schottky barrier is created due to the difference in
a) voltages
b) thickness c) work function d) density

Gallium arsenide crystals are grown from
a) boron oxide
b) silicon oxide c) silicon nitride d) boron nitride

Wafers in GaAs fabrication are thermally unstable.
a) true
b) false

Which devices are fabricated using planar process?
a) enhancement mode MESFET
b) depletion mode MESFET c) enhancement mode MOSFET d) depletion mode MOSFET

Formation of n-active layer is achieved by
a) indirent ion implantation
b) direct ion implantation c) liquifying d) wafering

The channel resistance is high for
a) source contact
b) drain contact c) gate contact d) source and drain contacts

Which was employed as the first level capping material?
a) SiO2
b) SiO c) Si3N4 d) Si2N4

What is Lithography?
a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip c) Process used to develop a metal layer on the chip d) Process used to produce the chip

Silicon oxide is patterned on a substrate using ____________
a) Physical lithography
b) Photolithography c) Chemical lithography d) Mechanical lithography

The ______ is used to reduce the resistivity of poly silicon.
a) Photo resist
b) Etching c) Doping impurities d) None of the mentioned

The isolated active areas are created by technique known as ___________
a) Etched field-oxide isolation
b) Local Oxidation of Silicon c) Etched field-oxide isolation or Local Oxidation of Silicon d) None of the mentioned