In orthogonal signal, all cross correlation coefficients are
a) One
b) Zero c) Negative d) None of the mentioned

The smaller the cross correlation, the ______ is the distance between the signal vectors.
a) More
b) Less c) Double d) Half

Biorthogonal set consists of
a) Orthogonal signals
b) Antipodal signals c) Combination of orthogonal and antipodal d) None of the mentioned

Which codes perform better?
a) Orthogonal
b) Biorthogonal c) Orthogonal & Biorthogonal d) None of the mentioned

Biorthogonal codes needs ________ bandwidth as orthogonal codes.
a) Equal
b) Double c) Half d) Triple

Which code requires minimum Eb/N0?
a) Orthogonal
b) Biorthogonal c) Simplex d) All of the mentioned

VLSI is an acronym for _________

Varying large Scale Integration Varying large Scale Integrity Very large Scale Integration None of the above

MOSFETs possess ________

A) Poor packing density B) Low packing density C) High packing density D) None of the above

_____ to form integrated circuit VLSI technology uses.

A) diodes B) buffers C) switches D) transistors

What is medium scale integration?

A) Ten logic gates B) Fifty logic gates C) Hundred logic gates D) Thousands of logic gates

Logic design of VLSI is used________

A) LIFO B) FIFO C) LILO D) FILO

Which type of MOSFET exhibits no current at zero gate voltage?

A) Depletion MOSFET B) Enhancement MOSFET C) Both A & B D) None of the above

MOS transistor structure is ________

A) symmetrical B) semi symmetrical C) non symmetrical D) pseudo symmetrical

The VLSI design flow starts with:

A) RTL synthesis B) Library mapping C) Product specifications D) None of the above

The difficulty in achieving high doping concentration leads to ____________
a) error in concentration
b) error in variation c) error in doping d) distribution error

_________ is used to deal with effect of variation.
a) chip level technique
b) logic level technique c) switch level technique d) system level technique

______ architecture is used to design VLSI.
a) system on a device
b) single open circuit c) system on a chip d) system on a circuit

Which provides higher integration density?
a) switch transistor logic
b) transistor buffer logic c) transistor transistor logic d) circuit level logic

Physical and electrical specification is given in ____________
a) architectural design
b) logic design c) system design d) functional design

Gate minimization technique is used to simplify the logic.
a) true
b) false

nMOS fabrication process is carried out in ____________
a) thin wafer of a single crystal
b) thin wafer of multiple crystals c) thick wafer of a single crystal d) thick wafer of multiple crystals