Network Block Device. Contribute to NetworkBlockDevice/nbd development by creating an account on GitHub.

A FPGA friendly 32 bit RISC-V CPU implementation. Contribute to SpinalHDL/VexRiscv development by creating an account on GitHub.

場效可程式化邏輯閘陣列（英語：field-programmable gate array，縮寫為FPGA），它以PAL、GAL、CPLD等可编程逻辑器件為技術基礎發展而成。作為特殊应用集成电路中的一种半定制电路，它既彌補全定制電路不足，又克服原有可编程逻辑控制器邏輯閘數有限的缺點。

开源指令集架构

The Open-Standard Instruction Set Architecture. RISC-V has 67 repositories available. Follow their code on GitHub.