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Daily Articles: π£ @ai_python_arxiv
5 of Latest Published Articles:
Artificial Intelligence
#ArtificialIntelligence
π The Art of Drafting: A Team-Oriented Hero Recommendation System for Multiplayer Online Battle Arena Games
π₯ Zhengxing Chen, Truong-Huy D Nguyen, Yuyu Xu, Chris Amato, Seth Cooper, Yizhou Sun, Magy Seif El-Nasr
π PDF
π Learning Social Conventions in Markov Games
π₯ Adam Lerer, Alexander Peysakhovich
π PDF
π Adversarial Exploration Strategy for Self-Supervised Imitation Learning
π₯ Zhang-Wei Hong, Tsu-Jui Fu, Tzu-Yun Shann, Yi-Hsiang Chang, Chun-Yi Lee
π PDF
π Complexity Results for Preference Aggregation over (m)CP-nets: Pareto and Majority Voting
π₯ Thomas Lukasiewicz, Enrico Malizia
π PDF
π Independence of Sources in Social Networks
π₯ Manel Chehibi, Mouna Chebbah, Arnaud Martin
π PDF
#ArtificialIntelligence
AI Python & arXiv Channel
Artificial Intelligence
#ArtificialIntelligence
π The Art of Drafting: A Team-Oriented Hero Recommendation System for Multiplayer Online Battle Arena Games
π₯ Zhengxing Chen, Truong-Huy D Nguyen, Yuyu Xu, Chris Amato, Seth Cooper, Yizhou Sun, Magy Seif El-Nasr
π PDF
π Learning Social Conventions in Markov Games
π₯ Adam Lerer, Alexander Peysakhovich
π PDF
π Adversarial Exploration Strategy for Self-Supervised Imitation Learning
π₯ Zhang-Wei Hong, Tsu-Jui Fu, Tzu-Yun Shann, Yi-Hsiang Chang, Chun-Yi Lee
π PDF
π Complexity Results for Preference Aggregation over (m)CP-nets: Pareto and Majority Voting
π₯ Thomas Lukasiewicz, Enrico Malizia
π PDF
π Independence of Sources in Social Networks
π₯ Manel Chehibi, Mouna Chebbah, Arnaud Martin
π PDF
#ArtificialIntelligence
AI Python & arXiv Channel
5 of Latest Published Articles:
Hardware Architecture
#HardwareArchitecture
π BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
π₯ Yaman Umuroglu, Lahiru Rasnayake, Magnus Sjalander
π PDF
π Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs
π₯ Thomas B. PreuΓer
π PDF
π LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels
π₯ Julian Stecklina, Thomas Prescher
π PDF
π A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB
π₯ Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham
π PDF
π RAPIDNN: In-Memory Deep Neural Network Acceleration Framework
π₯ Mohsen Imani, Mohammad Samragh, Yeseong Kim, Saransh Gupta, Farinaz Koushanfar, Tajana Rosing
π PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
π BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing
π₯ Yaman Umuroglu, Lahiru Rasnayake, Magnus Sjalander
π PDF
π Generic and Universal Parallel Matrix Summation with a Flexible Compression Goal for Xilinx FPGAs
π₯ Thomas B. PreuΓer
π PDF
π LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels
π₯ Julian Stecklina, Thomas Prescher
π PDF
π A 1.2-V 162.9-pJ/cycle Bitmap Index Creation Core with 0.31-pW/bit Standby Power on 65-nm SOTB
π₯ Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham
π PDF
π RAPIDNN: In-Memory Deep Neural Network Acceleration Framework
π₯ Mohsen Imani, Mohammad Samragh, Yeseong Kim, Saransh Gupta, Farinaz Koushanfar, Tajana Rosing
π PDF
#HardwareArchitecture
AI Python & arXiv Channel