5 of Latest Published Articles:
Artificial Intelligence
#ArtificialIntelligence
🗒 Scalable Tensor Completion with Nonconvex Regularization
👥 Quanming Yao
📗 PDF
🗒 NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference
👥 Mahdi Nazemi, Ghasem Pasandi, Massoud Pedram
📗 PDF
🗒 Data Science with Vadalog: Bridging Machine Learning and Reasoning
👥 Luigi Bellomarini, Ruslan R. Fayzrakhmanov, Georg Gottlob, Andrey Kravchenko, Eleonora Laurenza, Yavor Nenov, Stephane Reissfelder, Emanuel Sallinger, Evgeny Sherkhonov, Lianlong Wu
📗 PDF
🗒 The Vadalog System: Datalog-based Reasoning for Knowledge Graphs
👥 Luigi Bellomarini, Georg Gottlob, Emanuel Sallinger
📗 PDF
🗒 Multi-View Fuzzy Logic System with the Cooperation between Visible and Hidden Views
👥 Te Zhang, Zhaohong Deng, Dongrui Wu, Shitong Wang
📗 PDF
#ArtificialIntelligence
AI Python & arXiv Channel
Artificial Intelligence
#ArtificialIntelligence
🗒 Scalable Tensor Completion with Nonconvex Regularization
👥 Quanming Yao
🗒 NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference
👥 Mahdi Nazemi, Ghasem Pasandi, Massoud Pedram
🗒 Data Science with Vadalog: Bridging Machine Learning and Reasoning
👥 Luigi Bellomarini, Ruslan R. Fayzrakhmanov, Georg Gottlob, Andrey Kravchenko, Eleonora Laurenza, Yavor Nenov, Stephane Reissfelder, Emanuel Sallinger, Evgeny Sherkhonov, Lianlong Wu
🗒 The Vadalog System: Datalog-based Reasoning for Knowledge Graphs
👥 Luigi Bellomarini, Georg Gottlob, Emanuel Sallinger
🗒 Multi-View Fuzzy Logic System with the Cooperation between Visible and Hidden Views
👥 Te Zhang, Zhaohong Deng, Dongrui Wu, Shitong Wang
#ArtificialIntelligence
AI Python & arXiv Channel
5 of Latest Published Articles:
Hardware Architecture
#HardwareArchitecture
🗒 CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement
👥 Vinson Young, Sanjay Kariyappa, Moinuddin K. Qureshi
📗 PDF
🗒 Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
👥 Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
📗 PDF
🗒 Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs
👥 Tobias Strauch
📗 PDF
🗒 Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++
👥 Tobias Strauch
📗 PDF
🗒 Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
👥 Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
📗 PDF
#HardwareArchitecture
AI Python & arXiv Channel
Hardware Architecture
#HardwareArchitecture
🗒 CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement
👥 Vinson Young, Sanjay Kariyappa, Moinuddin K. Qureshi
🗒 Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
👥 Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu
🗒 Timing Driven C-Slow Retiming on RTL for MultiCores on FPGAs
👥 Tobias Strauch
🗒 Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++
👥 Tobias Strauch
🗒 Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation
👥 Yixin Luo, Saugata Ghose, Yu Cai, Erich F. Haratsch, Onur Mutlu
#HardwareArchitecture
AI Python & arXiv Channel