Note on Pennylane and "Train Classical, Deploy Quantum" method

https://colab.research.google.com/drive/1iouwEmx3GY6M6imBd87Sx65XW9b7en-Z?usp=sharing

#Wiser2026

Qiskit Summer school live:

https://gateway.on24.com/wcc/eh/5192571/category/146845/upcoming-sessions

red flags that recur in quantum coverage

Inside IBM Research

Qubit connectivity on the actual hardware matter a lot when designing the circuit. being aware of which qubits are directly connected helps us reduce additional depth that would have been added to make those qubit interact if they weren't next to each other.

The image is the connectivity map of the two IBM devices( Heron and Nighthawk)

The importance of layout lies in its direct impact on the quality and feasibility of quantum circuit execution. A poor layout occurs when logical qubits that need to interact in the circuit are mapped to physical qubits that are not directly connected in the hardware. In these cases, the compiler must insert additional SWAP operations to move quantum states between qubits, allowing the desired interaction to finally occur. These SWAP operations have multiple negative consequences: they increase circuit depth (the number of sequential gate layers), increase the total number of gates that must be executed, accumulate more error due to the imperfections of each additional gate, and reduce the fidelity of the final result due to quantum decoherence that occurs during the extra execution time.

Conversely, a good layout minimizes or eliminates the need for SWAP operations by intelligently assigning logical qubits that interact frequently to physical qubits that are directly connected in the hardware topology. This optimal mapping preserves the structure of the original circuit as much as possible, reducing transpilation overhead and maximizing the probability of obtaining accurate results. In variational algorithms such as QAOA, where circuit depth and gate fidelity are critical to performance, the difference between an optimal layout and a suboptimal one can determine the success or failure of the entire quantum experiment.

#Note

Efficient Long-Range Entanglement Using Dynamic Circuits

https://journals.aps.org/prxquantum/pdf/10.1103/PRXQuantum.5.030339

#paper

How to interpret quantum hardware specs

- Number of qubits: how many physical qubits the chip has. (Note: "programmable" = the ones you can run on, "physical" = total on the chip.)

- Basis gates: the only gates the hardware can natively run. Your code gets transpiled so it's expressed using just these.

- Readout error: the error during measurement. Lower is better.

- 1Q / 2Q gate error: the noise each gate adds. Two-qubit gates are ~10× noisier than single-qubit ones, so this is the number that judges a device.

- CLOPS (Circuit Layer Operations Per Second): how many gate layers run per second. Throughput, like classical computers. Higher = faster (not more accurate).

- T1 (energy relaxation): time for excited |1⟩ to decay to |0⟩.

- T2 (dephasing): time before phase coherence between |0⟩ and |1⟩ is lost.
The longer T1 and T2, the deeper the circuit you can run before noise wins.

(the image is one of IBM device from https://quantum.cloud.ibm.com/computers?limit=10 )

#Note

The Quantum Advantage Tracker is a community-driven platform that documents experimental demonstrations of quantum advantage. It allows researchers to explore existing results, compare approaches, and submit their own quantum advantage demonstrations.

#Note

Riverlane and Unitary Foundation Launch ‘Deltakit Community Fund’ to Accelerate Open-Source Quantum Error Correction

https://thequantuminsider.com/2026/07/28/riverlane-unitary-foundation-deltakit-community-fund/

#blogs

this is open till july 31

https://www.ibm.com/quantum/blog/qdc-application-2026

this looks interesting

https://en.wikipedia.org/wiki/Mechanistic_interpretability
https://mechinterp.com/