In Register Transfer Notation …. Operation is allowed

Single core computers have multiple processors

When these processors all reside on a single chip, the term …. computer is used.

Another prominent feature of contemporary computers is the use of multiple layers of memory, called …. Memory

A greater performance improvement may be obtained by using multiple levels of.....

level 1 cache …. to the core

n level cache is …. And …. n+1 level cache

in IAS computer IAS stands for

The memory of the IAS consists of 4,096 storage locations, called

In IAS architecture each word consisted of …. Bits

In IAS architecture Word formats. Each number is represented by a sign bit and a …. bit value

In IAS architecture each instruction consisting of …. bits consisted of operations code (opcode)

In IAS each instruction …. bits of address bit address designating one of the words in the memory

....Contains a word to be stored in memory or sent to the I/O unit, or is used to receive a word from memory or from the I/O unit

Specifies the address in memory of the word to be written from or read into the MBR

.....operates the IAS by fetching instructions from memory and executing them one at a time

Contains the 8 bit opcode instruction being executed

Employed to hold temporarily the righthand instruction from a word in memory.

Contains the address of the next instruction pair to be fetched from memory.

Employed to hold temporarily operands and results of ALU operations.

The IAS operates by repetitively performing an instruction cycle: …. steps