Short

I/O buses are shorter than processor-memory buses

Allow for many types of devices with varying bandwidths

Very design specific

high speed buses closely matched to memory system to maximize bandwidth (transfer of data)

Compatible with many different architecture

Is built into the chassis of the machine

connects the processor, the I/O devices, and the memory

Many computers have a hierarchy of buses (Two or more)

High performance systems often use all three types of buses

Devices are divided into master and slave categories

devices is one that initiates actions

is one that responds to requests by a master

In a very simple system the processor is the only one allowed to be the bus master

It is good in avoiding conflict, but it needs processor to be involved in every transaction uses the bus

In system with …. master device a bus arbitration is needed

Bus arbitration

A centralized arbiter selects who gets the bus

If collision (multi requests in the same time), the device must make another request

Instead of a central authority to get the bus, the devices themselves determine who has the height priority and get the bus

Fairness is not ensured (low priority devices may be starved out –never allowed to use the bus)