Processor can address cache memory

cache can address processor

cache and main memory can address each other

cache can address main memory

Main memory can address cache

Main memory and cache can transfer data between each other

After the processor issues load request to cache, it compares request address to … & see if there’s a match

Read block of data from main memory

Replace victim block of cache with new block

After comparing the request address to cache tag it immediately returns a copy of data from cache

found in cache

not in cache

After comparing the request address to cache tag it reads block of data from main memory then replace victim block in cache with new block and finally returns a copy of data from cache

A …. holds commonly used memory data

The number of data words that it can hold is called the

cache has a zero miss rate

Because it is impossible to predict the future with perfect accuracy, the cache must guess what data will be needed based on the past pattern of memory accesses

The cache exploits …. to achieve a low miss rate

means that the processor is likely to access a piece of data again soon if it has accessed that data recently

when the processor loads or stores data that is in the cache, the data is copied from main memory into the cache

means that, when the processor accesses a piece of data, it is also likely to access data in nearby memory locations