Bit Area => Very Small

Bit Area => Large (>= 6T)

Speed => Fast (Larger Arrays are slower)

Speed => Slow (Multiple Steps)

Speed => Very Slow (Mechanical)

Speed Hierarchy: Virtual Memory ---> Main memory ---> Cache memory ---> CPU registers

Capacity Hierarchy: Virtual Memory > Main memory > Cache memory > CPU registers

Processor and cache can address each other

Processor and cache can transfer data between each other

Processor can address cache memory

cache can address processor

cache and main memory can address each other

cache can address main memory

Main memory can address cache

Main memory and cache can transfer data between each other

After the processor issues load request to cache, it compares request address to … & see if there’s a match

Read block of data from main memory

Replace victim block of cache with new block

After comparing the request address to cache tag it immediately returns a copy of data from cache