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القناة الأساسية
@stepbystep001

ومـما زادني شـرفـاً وتـيــهـاً
وكدت بأخمصي أطأ الـثريا
دخولي تحت قولك يا عبادي
وأن صـيَّرت أحمد لي نـبيـا
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Access time is measured by cycles
Anonymous Quiz
90%
T
10%
F
Miss Rate is measured by percentage
Anonymous Quiz
90%
T
10%
F
An 11-cycle average memory access time means that the processor spends …. cycles waiting for data for every … cycle actually using that data
Anonymous Quiz
7%
10 – 11
56%
10 – 1
19%
1 – 10
20%
11 – 1
Data stable while powered
Anonymous Quiz
45%
SRAM
19%
DRAM
36%
Disk
Must be periodically refreshed
Anonymous Quiz
10%
SRAM
87%
DRAM
3%
Disk
Non volatile
Anonymous Quiz
6%
SRAM
3%
DRAM
91%
Disk
Inexpensive
Anonymous Quiz
15%
SRAM
53%
DRAM
31%
Disk
Very Cheap
Anonymous Quiz
8%
SRAM
15%
DRAM
77%
Disk
expensive
Anonymous Quiz
91%
SRAM
7%
DRAM
2%
Disk
Bit Area => Small (1T & capacitor)
Anonymous Quiz
17%
SRAM
71%
DRAM
12%
Disk
Bit Area => Very Small
Anonymous Quiz
29%
SRAM
16%
DRAM
54%
Disk
Bit Area => Large (>= 6T)
Anonymous Quiz
80%
SRAM
10%
DRAM
10%
Disk
Speed => Fast (Larger Arrays are slower)
Anonymous Quiz
84%
SRAM
13%
DRAM
2%
Disk
Speed => Slow (Multiple Steps)
Anonymous Quiz
3%
SRAM
82%
DRAM
15%
Disk
Speed => Very Slow (Mechanical)
Anonymous Quiz
3%
SRAM
5%
DRAM
92%
Disk
Speed Hierarchy: Virtual Memory ---> Main memory ---> Cache memory ---> CPU registers
Anonymous Quiz
41%
T
59%
F
Capacity Hierarchy: Virtual Memory > Main memory > Cache memory > CPU registers
Anonymous Quiz
73%
T
27%
F
تم تحويل جميع اسئلة المحاضره 2 Arch ولله الحمد.
بسم الله والصلاة والسلام على رسول الله ﷺ.
COA Lecture 3
Processor and cache can address each other
Anonymous Quiz
82%
T
18%
F