data values are transferred from the capacitor to the bit line

data values are transferred from the bit line to the capacitor

When the address line is selected, the charge stored on the capacitor is fed out onto a bit line

…. destroys the bit value stored on the capacitor, so the data word must be restored (rewritten) after each read

Even when DRAM is not read, the contents must not to be refreshed (read and rewritten) every few milliseconds, because the charge on the capacitor gradually leaks away

A voltage signal is applied to the bit line(1 for high, 0 for low)

A signal is then applied to the address line, allowing a charge to be transferred to the capacitor

a DRAM requires the supporting refresh circuitry

…. requires the supporting refresh circuitry

SRAM is static because stored bits do not need to be refreshed

in SRAM The data bit is stored on cross-coupled inverters

if noise degrades the value of the stored bit, the cross-coupled inverters restore the value

DRAM cell is … and … than SRAM cell

DRAM is … dense and … expensive than SRAM

smaller cells=… cells per unit area

SRAMs (used for cache memory ) are generally faster than DRAMs (used for main memory)

SRAMs, and DRAMs are all volatile memories

Different memory technologies, such as DRAM, SRAM, and hard drives, offer trade-offs in capacity, speed, and cost

To deal with this disparity, computer systems use a combination of memory types to provide the best performance at the best cost. This approach is called

The faster memory is, the more expensive it is per bit of storage

Main memory is typically built from DRAM, which is significantly faster than the processor.