Which condition causes the oVerflow (V) status flag to be set in the ALU?
Anonymous Quiz
11%
A. When the carry-out from the most significant bit of the adder is 1.
61%
B. When adding two numbers of the same sign and the result has the opposite sign.
11%
C. When the result of any operation is exactly zero.
18%
D. When the result of an operation is a negative number
How is the Zero (Z) status flag generated from the ALU's result output?
Anonymous Quiz
50%
A. By performing a NOR operation on all bits of the result.
7%
B. By checking if the least significant bit of the result is 0.
36%
C. By checking if the oVerflow (V) and Carry (C) flags are both 0.
7%
D. By connecting it to the most significant bit of the result.
For a signed comparison to determine if A < B, the ALU calculates A - B and checks the status flags. Which flag condition correctly indicates 'less than'?
Anonymous Quiz
11%
A. The Z flag is 1.
25%
B. The N flag is 1.
50%
C. the result of N XOR V is 1.
14%
D. The C flag is 0
In the IEEE 754 single-precision (32-bit) format, what value is stored in the 8-bit exponent field to represent a number with a true exponent of 5?
Anonymous Quiz
44%
A.132
19%
B.122
33%
C.127
4%
D. 5
According to the IEEE 754 standard, how is Not a Number (NaN) represented in a single-precision floating-point number?
Anonymous Quiz
16%
A.The sign bit is 1, and all exponent and fraction bits are 1.
36%
B.The exponent field is set to all 1s and the fraction field is all 0s.
48%
C.The exponent field is set to all 1s and the fraction field is all non-zero.
In the context of a RISC-V pipeline, during which stage is a memory operand accessed for a load or store instruction?
Anonymous Quiz
12%
A. EX
20%
B. WB
20%
C. ID
48%
D. MEM
A situation where a planned instruction cannot execute in the proper clock cycle because a necessary hardware resource is already in use by another instruction is known as a:
Anonymous Quiz
27%
A. Control hazard
58%
B. Structural hazard
15%
C. Data hazard
Which of the following correctly identifies the five stages of the pipelined RISC-V processor in the correct sequence?
C. Fetch, Decode, Memory, Execute,
C. Fetch, Decode, Memory, Execute,
Anonymous Quiz
8%
A. Decode, Fetch, Execute, Writeback, Memory
12%
B. Fetch, Execute, Decode, Memory, Writeback
31%
C. Fetch, Decode, Memory, Execute, Writeback
50%
D. Fetch, Decode, Execute, Memory, Writeback
If a processor performs 4,000 memory accesses (loads and stores) during a program's execution, and 3,500 of these requests are found in the cache, what is the cache's miss rate?
Anonymous Quiz
11%
A. 500
22%
B. 14.2%
59%
C. 12.5%
7%
D. 87.5%
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